Developing Micro-Columns of Test Sockets to Enable Processor Validation Signals
This study addresses the challenge of optimizing the interconnection between processors and micro contact pads (uADC) during the validation process. The aim is to leverage debug signals to measure and diagnose interfaces in the processors, using a debug interposer as a measurement interface. The uADCs represent an alternative for incorporating additional contacts in validation by occupying a space between commercial processor pads. However, the development of uADCs faces technological challenges such as reducing the contact area and ensuring electrical resistance stability. To address these challenges, the use of an inter-connection socket (SDI) with micro–column interconnect (uCDI) technology, capable of meeting the required conductivity, is proposed. Experimental results demonstrate electrical resistivity measurements below one hundred ohms which is the maximum accepted value within the context of processor validation. The implementation of uADCs and the use of SDI with uCDI offer advantages in the processor validation process by providing access to previously inaccessible signals, setting a precedent for future research in contact miniaturization in commercial products.
Keywords: micro contact pads, processor, debug interposer, interconnect socket, interconnection microcolumns.
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